Electrostatic discharge (ESD) is an ever present concern in the design, manufacture and handling of integrated circuits (ICs). An electrostatic voltage, which can be many thousands of volts, can appear on an input, output or power pin of a device. The static discharge occurs when the device is approached by a charged human or equipment. If the voltage from an ESD strike is passed into the integrated circuit device, permanent and destructive harm including gate oxide rupture of MOS transistors coupled to the pins can occur. The highest risk for ESD “strikes” is during handling and packaging operations when the die is exposed to potentially static charged machines or humans that come into contact with the device and the integrated circuit is not powered. Additional risk of ESD strikes can occur at other times when the integrated circuit is not powered.
Three common models used to describe the types of ESD events are the “human body model” (HBM), the “machine model” (MM) and the “charged device model” (CDM). In comparing the models, an ESD strike from the HBM has the longest duration of 100 nS, MM ESD strikes have comparatively faster rise times and more peak current, and CDM ESD strikes have the fastest rise time, less than 500 pS.
To prevent destructive harm from occurring due to ESD events during manufacturing, assembly, and handling of the IC, most integrated circuits have ESD protection circuits and structures formed around the conductors and near the fragile devices coupled to the input, output and power pins. These ESD structures provide low resistance paths that direct current from an input, output or power pin to a ground or positive power rail during an ESD event, and direct the current from the vulnerable internal circuitry.
Although ESD protection is essential when the integrated circuit device is unpowered, in conventional ESD protection structures the functional circuit design has to be arranged to avoid inadvertently triggering the ESD protection circuitry due to the normal switching operations of the circuit. If an ESD circuit is triggered inadvertently by normal transistor switching during circuit operation, the voltage clamping action of the ESD protection will cause erroneous operation of the integrated circuit. This requirement often puts undesirable limitations on the switching speed or slew rate of the primary function circuits. To avoid inadvertent triggering of the ESD protection, the speed and rise time for signals driven by the functional circuit have to be lowered and modified, degrading performance that the circuit could otherwise achieve.
FIG. 1 depicts a conventional solution for clamping ESD pulses using diodes in conjunction with a supply rail clamp. In the circuit 100, a low drop out regulator/power amplifier (LDO/PA) is biased with power supplies coupled to the pins or pads VIN and VSS. The ESD protection is effective for the device when it is a packaged integrated circuit and also when the circuit is within a bare die form, or as a die within a completed wafer that has not been prepared for packaging. Power rails VIN rail and VSS rail are coupled to the pins and carry the power supply voltages VIN, VSS into the device. The VIN and VSS supply rails are coupled to the external terminals for receiving a positive power supply voltage and a ground for negative supply voltage in operation. ESD protection is provided for the VIN and VSS rails by the circuit labeled “Rail Clamp 1.” Rail Clamp 1 consists of a resistor-capacitor (RC) detector circuit 112 and a voltage clamp (which can be implemented by a MOSFET transistor, alternatively, other transistor types can be used). The voltage clamp ESD MOSFET 1 provides a low resistance path between the VIN supply rail and the VSS supply rails when it is enabled by the clamp enable signal (cl_en). When triggered by an increasing voltage between VIN and VSS that charges the capacitor C through resistor R, the detector circuit 112 produces a pulse on the signal clamp enable cl_en. The cl_en pulse duration depends on the values selected for the resistor R and capacitor C for a particular design, as these form a time constant proportional to the product R*C. In this conventional solution, the LDO/PA output pin OUT is protected from ESD events by diodes D1 and D2 and the rail clamp. A high positive or negative voltage at the output pin OUT will forward bias one of the diodes D1 or D2, and couple the pin OUT to either the VIN supply rail (positive ESD voltage) or the VSS supply rail (negative ESD voltage), triggering the rail clamp and thus protecting the LDO/PA or other circuitry coupled to the pin OUT from damaging current during an ESD strike.
When no power is applied to the device 100, a negative ESD pulse at the pin OUT with respect to VSS will be shunted by the diode D2 to the VSS supply rail, because D2 becomes forward biased. A positive ESD pulse propagating between the VIN and VSS inputs will cause the RC Detector 112 to trigger, thus sending an enable pulse on the cl_en line. The pulse on the cl_en line activates the ESD MOSFET 1 that then clamps the VIN supply rail to VSS, safely shunting the ESD current. The clamping action protects the transistors within the LDO/PA that are coupled to the VIN or VSS supply rail from ESD damage by limiting the voltage across these rails. When a positive ESD pulse with respect to VSS occurs on the OUT line, the voltage on OUT will increase, forward biasing diode D1, coupling the rising ESD voltage to the VIN supply rail, and eventually triggering Rail Clamp 1. Note that the OUT line will experience a higher clamped voltage than that occurring directly across Rail Clamp 1 due to the additional voltage drop across diode D1 and the rail bus metal resistance. The higher voltage experienced by OUT carries an additional risk of damage to the circuitry connected to the OUT line. Note that when the circuit 100 is powered, the ESD protection circuitry in Rail Clamp 1 is still active. A rapid voltage rise on the power pin VIN can inadvertently trigger the RC detector 112. During power up operations, care must be taken to ensure this does not occur.
FIG. 2 depicts a conventional low clamping voltage ESD protection solution utilizing dual rail clamps, labeled Rail Clamp 1 and Rail Clamp 2. In the device 200, which can be an integrated circuit or a bare die, a low drop out regulator/power amplifier (LDO/PA) is biased with power supplied to the VIN supply rail and the VSS supply rail at pins VIN and VSS. ESD protection is provided for the VIN and VSS supply rails by Rail Clamp 1. As in FIG. 1, Rail Clamp 1 consists of a detector circuit 212 paired with a voltage clamp (ESD MOSFET 1, which can be implemented using a MOSFET as indicated in the figure, alternatively other transistor device types such as bipolar transistors can be used as the voltage clamp). When the detector circuit 212 is triggered, the detector circuit produces a pulse on the clamp enable (cl_en) line which activates ESD MOSFET 1. The duration of the enable pulse is determined by the values selected for the resistor R and capacitor C. The voltage clamping circuit ESD MOSFET 1 couples the VIN supply rail to the VSS supply rail, preventing damaging current from harming the components within LDO/PA, such as MOS transistors that are coupled to the VIN supply rail.
When no supply power is applied to the circuit 200, the VIN supply rail and VSS supply rail are protected from a positive ESD pulse by Rail Clamp 1, which operates as described hereinabove with respect to FIG. 1. When a positive ESD pulse with respect to VSS occurs on the OUT line, the fast rising ESD pulse triggers the detector circuit 213 of Rail Clamp 2. The detector circuit 213 then transmits a pulse on the clamp enable signal cl_en2 to voltage clamp ESD MOSFET 2. Voltage clamp ESD MOSFET 2 clamps the pin OUT to the VSS supply rail. The clamped voltage can be near 1 volt. This clamped ESD voltage is a reduced maximum clamping voltage and thus improved ESD protection at the pin or pad OUT (when compared to the maximum clamping voltage using the FIG. 1 arrangement described hereinabove). The improved ESD protection is because the clamping action does not need to occur through a diode and VIN/VSS rail bus resistance. The improved ESD protection comes at the cost of functional performance for signals connected to OUT. More importantly, the operations of the functional circuitry such as the LDO/PA circuit also have to be modified to avoid inadvertent ESD triggers. The ESD protection remains active when the device is powered and operating. A fast rising voltage at the output pin OUT can trigger the RC detector 213, and the design performance for the amplifier LDO/PA has to be degraded using slew rate control or other measures to ensure this does not occur. Performance of the LDO/PA circuit is therefore degraded.
FIGS. 3A and 3B depict a simulated voltage response and a simulated current response of the low clamping voltage ESD solution of FIG. 2, and the graphs illustrate its limitations during functional operation. The vertical axis in graph 300 of FIG. 3A is in volts, with magnitude increasing from the origin. The vertical axis in graph 310 of FIG. 3B is current in milliamps with magnitude increasing from the origin. The horizontal axis of both FIGS. 3A and 3B is time in microseconds (uS) for graphs 300 and 310, with increasing time moving from the origin to the right.
In FIG. 3A, voltage waveform 302 is a simulated input enable signal to the LDO/PA. Waveform 304 is the simulated voltage at terminal OUT from the LDO/PA in response to the input waveform 302. Waveform 314 is the current flowing in the voltage clamp ESD MOSFET 2 within Rail Clamp 2 of FIG. 2 in response to the LDO/PA output waveform 304.
With power applied to the circuit 200 and enabled by the enable signal of waveform 302, the desired functional LDO/PA output of waveform 304 should reflect a simple voltage ramp from 0V to 1.5V. Instead of the desired voltage step, voltage waveform 304 shows the voltage clamping action of the ESD MOSFET in region 306. Waveform 314 shows current flowing through the ESD MOSFET 2 in region 316. Current flowing in the region 316 indicates that the fast rising voltage output 304 causes ESD detection circuit 213 to trigger. Thus, the circuit which provides desirable protection in an ESD event may introduce undesirable effects in normal operation. FIGS. 3A and 3B illustrate the undesirable effects of inadvertent triggering of the low clamping voltage ESD protection circuit Rail Clamp 2 during operation of the circuit 200.